Insulation sidewall spacers provide electrical separation between conductive regions in a semiconductor structure. One prior art method of forming insulation sidewall spacers (defined below) is described in U.S. Pat. No. 4,234,362 issued to Riseman on Nov. 18, 1980 which is incorporated herein by reference. In the Riseman method first a semiconductor structure S-1 is formed having "substantially horizontal surfaces" S-2 and "substantially vertical surfaces" S-3 as shown in FIG. 1. A conformal insulation layer S-4 is then formed on the semiconductor structure of FIG. 1 as shown in FIG. 2. Insulation layer S-4 may be one of several insulating materials such as silicon dioxide, silicon nitride, aluminum oxide, or combinations of these materials. Riseman states that the structure shown in FIG. 2 is then placed in a reactive ion etching ambient where the insulation layer S-4 is substantially removed from the horizontal surfaces S-2 without significantly affecting the insulation layer on the vertical regions S-3 in order to produce the vertical insulation regions called the insulation sidewall spacers S-5 shown in FIG. 3. These insulation sidewall spacers S-5 provide electrical separation between conductive regions in the semiconductor structure, for example between N.sup.+ emitter region S-6 and polycrystalline silicon regions S-7 shown in FIG. 3. Riseman further states that the desired thickness of insulation sidewall spacers S-5 is the thickness of the conformal insulation layer S-4 on the horizontal surfaces S-2 of semiconductor structure S-1. The thickness of the conformal layer is chosen for device design purposes such as emitter-base separation, and depends on the particular insulator used. Riseman suggests a conformal insulator layer having a thickness between 500 Angstroms and 20,000 Angstroms. A thickness of less than 500 Angstroms may lead to an electrical short circuit between conductive regions.
Later work by Riseman and others shows that the relationship between the thickness of the conformal layer and the thickness (width) of the sidewall spacer is more complex than is stated in the '362 patent. In Abstract No. 233, Sidewall Spacer Technology, P. J. Tsang, J. F. Shepard, and J. Riseman, IBM Corporation, Hopewell Junction, N.Y., which is incorporated herein by reference, the authors determined that there are three major factors that affect the final dimension and geometric configuration of an insulation sidewall spacer:
(i) the Chemical Vapor Deposition (CVD) film step coverage, Fsc;
(ii) the etching directionality and etch uniformity of the reactive-ion-etching (RIE) system (the system includes apparatus and etchant gas) used, Fe; and
(iii) a geometric factor, which is related to the surface topography of the sample before and after CVD coating, Fg.
Sidewall Spacer Technology concentrates on the geometric factor, Fg, since the first two factors, Fsc and Fe, are inherent properties of the deposition and etching reactors and are fixed. FIGS. 4a and 4b illustrate the parameters considered by the authors in formulating their geometric model under the assumptions that:
(i) the CVD is conformal, i.e., the deposited film assumes the shape of the underlying structure;
(ii) the CVD deposition resulted in a rounding of the upper corner of the step with the radius (r) of the curvature being equal to the film thickness (d), and centered at the upper corner of the step (as shown in FIG. 4a) and,
(iii) the RIE is anisotropic.
As shown in FIG. 4a, .phi. is the angle that the edge of the pattern step makes with the vertical, d is the thickness of the CVD coating, and h is the height of the step. FIG. 4b depicts the width of the spacer formed when the structure of FIG. 4a is subjected to an anisotropic RIE. The width of the spacer is given by the formula EQU W=F.sub.sc .times.F.sub.e .times.F.sub.g d.
The results reported in Sidewall Spacer Technology are reproduced in FIGS. 5a and 5b. An examination of FIGS. 5a and 5b show that unless the aspect ratio R=h/d is kept larger than 1.0 and angle .phi. equals zero (i.e. a vertical step) the width w of the sidewall produced will always be smaller than the deposited film thickness, i.e., (w/d)&lt;1. In addition, the variation of the width w caused by uncertainty of R, .phi., and overetch Oe will be larger if R.ltoreq.1.0 and .phi..gtoreq.0. It is suggested in Sidewall Spacer Technology that for most device applications a sidewall spacer having a width w that is as close as possible to the thickness d of the CVD layer is desired. For these purposes a vertical step and an aspect ratio of 1.5 is recommended, so that the width of the spacer is not sensitive to overetch, as shown in FIG. 5a.
Vertical walled polycrystalline silicon gates for MOS devices can be provided with a sidewall oxide spacer or with a multiple sidewall oxide spacer as shown in New Edge-Defined Vertical-Etch Approaches For Submicro meter MOSFET Fabrication, W. R. Hunter, T. C. Holloway, P. K. Chatterjee, and A. F. Tasch, Jr., IEEE-IEDM Tech. Dig., pp. 764-67 (1980), which is incorporated herein by reference.
In Fabrication of High-Performance LDDFETS With Oxide Sidewall-Spacer Technology, Paul J. Tsang, Seiki Ogura, William W. Walker, Joseph F. Shepard, and Dale L. Critchlow, IEEE, Electron Devices, ED-29, pp. 590-96, April 1982, which is incorporated herein by reference, a process is described wherein oxide sidewall spacers S-10 are formed at each end of a dual layer gate stack as shown in FIG. 6. The dual layer gate stack S-11 consists of a layer of CVD silicon oxide S-12 deposited on a layer of polycrystalline silion S-13. Gate oxide layer S-14 lies between the gate stack S-11 and the substrate S-15. Reactive ion etching (RIE) is used to etch both the oxide S-12 and the polycrystalline silicon S-13 so that vertical sides of the silicon dioxide/polycrystalline silicon gate stack are obtained before the oxide sidewall spacers are formed.
Of importance, in all of the above prior art techniques for forming an insulating sidewall spacer, it is nowhere disclosed or suggested that such spacers be formed in CMOS devices. In particular, it is not disclosed or suggested that the width of the insulation sidewall spacer be selected independently for NMOS and PMOS devices within a CMOS semiconductor structure.
Another method for forming insulation sidewall spacers is disclosed in copending U.S. patent application Ser. No. 6,595,796 filed Apr. 2, 1984 which is incorporated herein by reference. FIGS. 7 through 11 show one method of forming insulation sidewall spacers according to the teachings described in U.S. patent application Ser. No. 6,595,796.
FIG. 7 shows a semiconductor structure 20 including a silicon substrate 21 which is typically doped with either N type impurities or P type impurities. Substrate 21 is covered by a gate insulating layer 22 (typically silicon oxide or silicon nitride). In one embodiment, insulating layer 22 is a layer of silicon oxide thermally grown at 950.degree. C. in dry oxygen to a thickness of approximately 450 .ANG.. In another embodiment the gate insulating layer of silicon oxide or silicon nitride is formed by well known chemical vapor deposition (CVD). This insulating layer may be alternatively one or a combination of known insulating materials such as oxynitride or the like.
A first layer of polycrystalline silicon 23 is then deposited on the gate oxide layer 22 by low pressure (LP) CVD. Typically polycrystalline silicon 23 is doped, for example with phosphorous or other impurity, in order to increase its conductivity. Typically this doped polycrystalline silicon layer has a thickness between 2000 and 2500 Angstroms (.ANG.).
Second layer 24 of tungsten silicide (WSi.sub.2) is deposited on doped polycrystalline silicon layer 23 in a cold wall low pressure CVD reactor. Deposition is done with silane and tungsten hexafluoride diluted with helium at approximately 400.degree. C. Details of this process are described in Properties of Low Pressure CVD Tungsten Silicide as Related to IC Process Requirements, Brors, et al., Solid State Technology, pp. 183-86, April 1983, which is incorporated herein by reference. Layer 24 typically has a thickness between 1000 and 2500 .ANG. and is typically an insulating material, a silicide (such as tungsten silicide), or a refractory metal such as tungsten. Second layer 24 may be any material which has a lower etch rate than the underlying doped polycrystalline silicon for a selected etchant.
A layer of photoresist 25 is formed on second layer 24 and patterned by conventional techniques and the resulting structure is anisotropically etched to form structure 20 including multilayer stack 26 as shown in FIG. 7. The anisotropic etch is performed, for example, using plasma SF.sub.6. Structure 20 is then subjected to a plasma etch using CF.sub.4 or SF.sub.6 or a wet etch using HF:HNO.sub.3 :H.sub.2 O=1:60:60 in order to produce stack 27 shown in FIG. 8. In FIG. 8, second layer 24 is undercut by approximately 1000 to 2,500 .ANG. by the plasma etch or wet etch which etches second layer 24 at a slower rate than doped polycrystalline silicon layer 23. Plasma etchant CF.sub.4 or SF.sub.6 etches doped polycrystalline silicon layer 23 at a rate approximately twice as fast as second layer 24 when the second layer is tungsten silicide (WSi.sub.2)
The process steps described in FIGS. 7 and 8 can, if desired, be combined in a single step plasma etch. In one embodiment of this invention dual stack 27 is produced using a single step planar plasma etching system using SF.sub.6 as the main etching species.
Whether stack 27 is formed in one or two etching steps, the amount of undercut is easily controlled due to the known differential etch rates of the selected etchant on second layer 24 and on polycrystalline silicon layer 23. In one embodiment an overhang of approximately 1,200 .ANG. of tungsten silicide is provided by a single step planar plasma etching system using SF.sub.6 for approximately 1 minute. The etching characteristics of a dual layer consisting of silicide/polycrystalline-silicon is described in In Line Plasma Etch of Polysilicon and Molybdenum Silicide using SF.sub.6, P. Chang, et al., Kodak Microelectronics Seminar Proceedings, pp. 9-14, October 1980, which is incorporated herein by reference.
In one embodiment of the invention disclosed in co-pending U.S. patent application Ser. No. 6,595,796, stack 27 is used to form the gate of an insulated gate field effect transistor (IGFET). The gate stack shown in cross-section is one of many such gate stacks formed in a monolithic block of semiconductor material called a chip. In this embodiment photoresist layer 25 is stripped away using conventional techniques and a low dose (typically 1.times.10.sup.13 ions/cm.sup.2) of phosphorus ions is blanket implanted to form N.sup.- source/drain regions 42 as shown in FIGS. 9a and 9b. N.sup.- source/drain regions 42 are self aligned with the edges 24a and 24b of second layer 24. In those regions of the chip where silicon substrate 21 is doped with a P type dopant (shown as region 41 in FIG. 9a), semiconductor structure 40 is used to construct an N channel device. In those regions of the chip where silicon substrate 21 is doped with a N type dopant (shown as region 51 in FIG. 9b) semiconductor structure 50 is used to construct a P channel device. It is one of the features of one embodiment of the invention disclosed in co-pending U.S. patent application Ser. No. 6,595,796 that the low dose phosphorus ion implant is a blanket implant of the entire chip, which eliminates a traditional masking step. Traditionally a masking layer would be formed over the to-be-formed source/drain regions of N channel transistors during the implantation of low dose phosphorous ions in the source/drain regions of to-be-formed P channel transistors.
The phosphorus ion implant is followed by a high temperature (950.degree. C. to 1000.degree. C.) nitrogen annealing cycle to deepen the N.sup.- drain and source regions 42 to approximately 0.35 microns and to laterally diffuse these regions part way into the channel between them so that the edges of source/drain regions 42 are aligned with the edges 23a and 23b of polycrystalline silicon layer 23 as shown in FIG. 10. The peak dopant concentration in region 42 is then approximately 5.times.10.sup.17 atoms/cm.sup.3. The high temperature annealing cycle also reduces the sheet resistivity of the gate interconnection which comprises polycrystalline silicon layer 23 and silicide layer 24. For example, the sheet resistivity is approximately 2 to 3 ohms/square after 25 minutes of annealing, as compared with approximately 30 ohms/square before annealing. Low resistivity of the gate interconnection is required for the formation of high speed semiconductor devices whose channel width is of the order of 2 microns.
Following the annealing step, a conformal layer 61 of SiO.sub.2 approximately 3000 to 5000 .ANG. thick is formed on semiconductor structure 40 (FIG. 9a) or semiconductor structure 50 (FIG. 9b), for example, by chemical vapor deposition, to produce semiconductor structure 60 shown in FIG. 10. In other embodiments conformal layer 24 is silicon nitride, aluminum oxide, or other insulating material, or combinations of the above.
Next, the structure 60 is vertically etched to remove portions of oxide layers 61 and 22 to expose the doped source/drain regions 42 and to form structure 70 having vertical sidewall oxide spacers 71 which fill the regions under the ends of second layer 24 as shown in FIG. 11. The width W of the sidewall oxide spacer 71 as measured near the base of the spacer as shown in FIG. 11 is approximately 0.3 microns. In general the width of an insulation sidewall spacer formed in accordance with the teachings of this invention depends on the thickness of the conformal insulation layer, the differential etch rates of the second layer 24 and the underlying polycrystalline silicon layer 23, the etch time, and the over-etch time. Spacers having a width in the range of about 0.15 mm to 0.4 mm are produced by controlling these variables. The etchant used in one embodiment is CHF.sub.3 :O.sub.2 which has a high selectivity for etching insulating layer 22 as compared with silicon. For example, when insulating layer 22 is SiO.sub.2 the ratio of the etch rates of layer 22 to silicon is about 5:1 and when insulating layer 22 is silicon nitride, the ratio of the etch rates of layer 22 to silicon is about 2.5:1.
For the formation of N channel devices (i.e. where the underlying substrate region 41 is silicon doped with P type impurities), the vertical etching step is followed by an implant of an N type dopant such as arsenic to produce a peak concentration of approximately 1.times.10.sup.20 atoms/cm.sup.3 in the N.sup.+ regions 81 in source/drain regions 42 as shown in FIG. 12a. The N.sup.+ implant is required to insure good ohmic contact between these regions and later metallization layers (not shown) as described by Grove, Physics and Technology of Semiconductor Devices, John Wiley & Sons, (1967) at page 243, which is incorporated herein by reference. Of importance, sidewall spacers 71 at the edges of gate 23 shield from the N.sup.+ implants the portions of the N.sup.- region which underlies the sidewall spacers. This shielding provides lateral separation between edge 81a of the N.sup.+ regions 81 and edge 42a of the N.sup.- regions 42, as shown in FIG. 12a. The lateral separation is approximately the thickness of the sidewall spacer and reduces hot electron injection as is explained later.
The structure 74 shown in FIG. 12a is then annealed at a temperature of approximately 920.degree. C. in order to diffuse the N.sup.+ source/drain regions 81 to a junction depth of approximately 2000 .ANG. and thus form structure 80 shown in FIG. 13a. The anneal step also causes some lateral diffusion of the N.sup.+ regions 81 under the sidewall spacers 71 approximately equal to 85-90% of the vertical junction depth.
For the formation of P channel devices (i.e. where the underlying substrate region 51 is silicon doped with N type impurities), the vertical etching step is followed by an implant of a P type dopant, such as BF.sub.2, to produce a peak concentration of approximately 5.times.10.sup.19 atoms/cm.sup.3 in source/drain regions 91 formed in source/drain regions 42 as shown in FIG. 12b. The P type implantation is followed by an implant anneal at a temperature of approximately 920.degree. C. in order to form the P.sup.+ regions as shown in FIG. 13b. After annealing, the P.sup.+ source/drain regions 91 have a junction depth of approximately 4,000 .ANG..
The process steps to complete the formation of the P channel and N channel transistors, now depend on the composition of the second layer of the dual stack. For example, if the second layer 24 is silicon nitride Si.sub.3 N.sub.4, second layer 24 is removed using well known techniques (such as etching with hot phosphoric acid H.sub.3 PO.sub.4) and a noble metal such as platinum or a refractory metal such as titanium is deposited, which is then sintered to react with the top portion of the polycrystalline silicon layer 23, and with the top portion of N.sup.+ and P.sup.+ source/drain regions 81 and 91, respectively, to form layer 101 of platinum silicide, PtSi. The unreacted metal is removed using well known wet chemical solution (such as etching platinum with hot aqua regia) to form the P channel and N channel transistors 100 and 110 respectively, as shown in FIG. 14a and 14b.
If the second layer 24 is silicide, second layer 24 is not removed and platinum is deposited on semiconductor structures 80 and 90, shown in FIGS. 13a and 13b, and sintered to react with the top portions of N.sup.+ and P.sup.+ regions 81 and 91, respectively in order to form platinum silicide layer 101 of transistors 120 and 130 as shown in FIGS. 15a and 15b, respectively.
Transistors formed by the above process, using overhang induced sidewall spacers as exemplified in FIGS. 14a, 14b, 15a, and 15b, have several advantages over transistors with sidewall spacers formed by prior art methods.
First, the width, W, of the oxide spacer 71 (as measured near the bottom of spacer 71 as shown in FIG. 11) is principally controlled using the method of the present invention by controlling the degree of undercutting, which depends on the differential etch rates for second layer 24 and underlying doped polycrystalline silicon layer 23, the etch time, and the over etch time, and the thickness of the conformal oxide layer. The width of the oxide spacer formed by prior art methods depends on the geometric factors described in Sidewall Spacer Technology above, including the aspect ratio of the pattern step and the angle that the edge of the pattern step makes with the vertical, as well as the thickness of the CVD layer and over-etch time.
Second, the width, W, of the oxide spacer (as measured near the bottom of the spacer 71) is less sensitive to over etch time of the RIE and to the thickness of the CVD layer 61 than prior art methods as exemplified in Sidewall Spacer Technology, above, due to the protective overhang of second layer 24 as shown in FIG. 11.
Third, Miller capacitance is reduced in transistors having sidewall spacers formed according to this invention. This is illustrated in FIGS. 16a and 16b. FIG. 16a shows an N channel transistor 140 formed using prior art sidewall spacers. The Miller capacitance between the right end 143 of the dual stack gate comprising layer 121 and doped polycrystalline layer 23 and the N.sup.- region 42 beneath end 143 is inversely proportional to the distance d between the bottom surface 23c of right end 143 and the surface 42a of N.sup.- region 42. A parallel statement is true for left end 142. On the other hand, when sidewall spacers 71 are formed in accordance with the present invention, the Miller capacitance between the right end 153 of layer 121 and the N.sup.- region 42 beneath end 153 is inversely proportional to the distance d' between the bottom surface 121c of layer 121 and the surface 42a of N.sup.- region 42. A parallel statement is true for left end 152 of layer 121. Since d' is greater than d by the thickness of layer 23, Miller capacitance is reduced as compared with the Miller capacitance provided by prior art structures. Of importance, it is neither disclosed nor suggested by Riesman or in co-pending U.S. patent application Ser. No. 6,595,796 that the width of the insulation sidewall spacer be selected independently for NMOS and PMOS devices within a CMOS semiconductor structure.
As explained below, applicants have discovered that certain parameters for NMOS and PMOS devices in a CMOS integrated cirucit can be enhanced by constructing sidewall spacers for NMOS devices having greater width than sidewall spacers for PMOS devices within a CMOS integrated circuit.